Logic and memory device integration

ABSTRACT

Memory devices are adapted for direct interface or virtual integration with a processor or other logic device through a local bus and isolated from a system bus. Such memory devices are capable of lower power requirements and reduced size due in part to the elimination of certain redundant circuitry. Direct interfacing through the local bus facilitates the elimination or reduction of input/output (I/O) buffer circuitry by eliminating the need to step up to and step down from typical system bus voltage levels. Communication between the memory device and a separate logic device occurs across the local bus at voltage levels compatible with internal logic levels of the memory device.

RELATED APPLICATIONS

This application is a Continuation of U.S. application Ser. No. 09/940,259, filed Aug. 27, 2001, titled “LOGIC AND MEMORY DEVICE INTEGRATION” (allowed), which claims priority to Italian Patent Application Serial No. RM2000A000671, filed Dec. 15, 2000, titled “LOGIC AND MEMORY DEVICE INTEGRATION,” now Italian Patent No. 01316025, issued Mar. 26, 2003, which are commonly assigned and incorporated herein by reference.

TECHNICAL FIELD OF THE INVENTION

The present invention relates generally to semiconductor memory devices, and in particular, the present invention relates to semiconductor memory devices designed for integration with a processor or other logic device and systems produced therefrom.

BACKGROUND OF THE INVENTION

Electronic information handling or computerized systems, whether large machines, microcomputers or small handheld devices, require memory for storing data and program instructions. Various memory systems have been developed over the years to address the evolving needs of information handling systems. One such memory system includes semiconductor memory devices.

Semiconductor memory devices are rapidly-accessible memory devices. In a semiconductor memory device, the time required for storing and retrieving information generally is independent of the physical location of the information within the memory device. Semiconductor memory devices typically store information in a large array of cells. Data and status information of the memory device are provided to external devices through a set of DQ or data signal lines.

One particular form of semiconductor memory device is a non-volatile memory referred to as flash memory. Flash memory includes an array of memory cells made up of floating-gate transistors. A charge stored on the floating gate of the transistor determines the threshold voltage of the transistor. Various sensing methods can be used to detect the threshold voltage and thus determine the data value associated with an individual memory cell.

Computer, communication and industrial applications are driving the demand for memory devices in a variety of electronic systems. Specialized portable devices are consuming large quantities of flash memory and are continually pushing for lower voltages and higher densities to decrease power requirements, reduce size and increase functionality. Such portable devices include digital cellular or other wireless communication applications, digital cameras, audio recorders, personal digital assistants (PDAs) and test equipment.

In system applications requiring integration of logic devices and memory devices, three approaches are known. A first approach is to combine the logic device and the memory device in a single application-specific integrated circuit (ASIC) chip using a low-cost memory process. Such an approach is a low-cost alternative, but memory processes lack the metal layers and circuit complexity necessary to produce a high-performance logic device. Thus, such an ASIC provides relatively limited performance of the logic core.

A second approach is to combine the logic device and the memory device in a single-chip ASIC chip using a more sophisticated logic process providing for more metal layers and masks. While more expensive than the first approach, the logic process supports high-performance logic cores. In either of these approaches, the flexibility of the ASIC is limited as the functionality of the logic core and the size of the memory device are fixed. Modifications in response to market demands or new technologies generally require extensive retooling whether the modification affects only the memory portion or the logic portion of the ASIC. In addition, for related systems differing only in the amount of memory provided, separate ASICs would be required for each system.

FIG. 1A is a simplified block diagram of an electronic system 100 produced as a single-chip ASIC and coupled to a system bus 150. The electronic system 100 generally includes a memory core block 110 containing the memory cells and sensing circuitry; a control, logic and interconnect block 112; an analog block 114 providing the various internal voltage potentials from the supply potential; a logic core block 116; a static random access memory (SRAM) block 118 for caching data between the logic core block 116 and the memory core block 110; an input/output (I/O) block 120 for interfacing with the system bus 150; and often a customer-specific block 122 containing customer-specific functionality for the ASIC. It is noted that FIG. 1A is an abstraction of an electronic system and that the physical location and relative sizing of the individual blocks in the figure are not necessarily representative of an actual electronic system.

To provide more flexibility, albeit at increased cost, size and power requirements, a third approach to integrating a logic device and a memory device uses a separate logic device and a separate memory device. In this manner, the memory device and the logic device each can be produced using a process optimized for the particular device. Furthermore, responding to changing markets or new technology is relatively easy, in that only the relevant portion need be altered. In addition, related systems differing only in the amount of memory provided may be produced simply by substituting the appropriate memory device.

FIG. 1B is a simplified block diagram of an electronic system 100 having a memory device 102 and a logic device 104 each coupled to a system bus 150. The memory device 102 generally includes a memory core block 110 containing the memory cells and sensing circuitry; a control, logic and interconnect block 112; an analog block 114 providing the various internal voltage potentials from the supply potential; and an I/O block 124 for interfacing with the system bus 150. The logic device 104 generally includes a logic core block 116; a static random access memory (SRAM) block 118 for caching data between the logic core block 116 and the memory core block 110 of the memory device 102; an input/output (I/O) block 120 for interfacing with the system bus 150; and often a customer-specific block 122 containing customer-specific functionality for the logic device 104. An electronic system of the type shown in FIG. 1B may require 5-10% additional semiconductor real estate over an equivalent system of the type shown in FIG. 1A, due to the redundancy of the I/O circuitry. It is noted that FIG. 1B is an abstraction of an electronic system and that the physical location and relative sizing of the individual blocks or semiconductor chips in the figure are not necessarily representative of an actual electronic system.

For the reasons stated above, and for other reasons stated below that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for the integration of memory devices and logic devices supporting system flexibility, lower power requirements and reduced size.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a simplified block diagram of an electronic system produced as a single-chip ASIC and coupled to a system bus.

FIG. 1B is a simplified block diagram of an electronic system having a memory device and a logic device each coupled to a system bus.

FIG. 2A is a simplified block diagram of an electronic system having a memory device and a logic device, wherein the memory device is coupled to the logic device through a local bus.

FIG. 2B is a functional block diagram of a memory device as part of an electronic system having a memory device and a logic device, wherein the memory device is coupled to the logic device through a local bus.

FIGS. 3A-3C are a top, side and bottom view, respectively, of an electronic system as a stacked package, wherein the electronic system has a memory device coupled to a logic device through a local bus.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description of the present embodiments, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that process, electrical or mechanical changes may be made without departing from the scope of the present invention. The terms wafer or substrate used in the following description includes any base semiconductor structure. Examples include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of a silicon supported by a base semiconductor structure, as well as other semiconductor structures well known to one skilled in the art. Furthermore, when reference is made to a wafer or substrate in the following description, previous process steps may have been utilized to form regions/junctions in the base semiconductor structure, and the terms wafer and substrate include the underlying layers containing such regions/junctions. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims and equivalents thereof.

The various embodiments of the invention relate to the integration of a logic device and a memory device. Memory devices of various embodiments are adapted for communication directly with a logic device across a local bus. Memory devices of the various embodiments may include non-buffered devices. The local bus is dedicated to bi-directional communication between the logic device and the memory device. Voltages on the local bus are substantially at internal logic levels of the memory device.

For one embodiment, the local bus includes a plurality of direct connections between the memory device and the logic device. For a further embodiment, each direct connection of the local bus is a wire bond connection between a bonding pad on the memory device and a bonding pad on the logic device. For an alternate embodiment, each direct connection of the local bus is a solder bump connection between a bonding pad on the memory device and a bonding pad on the logic device. For another embodiment, each direct connection is dedicated to communication exclusively between a single bonding pad or other coupling area on the memory device and a single bonding pad or other coupling area on the logic device. The local bus is distinct and isolated from the system bus.

Use of a dedicated local bus between a memory device and a logic device facilitates elimination or reduction of buffer circuitry on the memory device. Input buffer circuitry adapted for level translation is normally included in a memory device to protect the device from voltage levels of a system bus. Output buffer circuitry adapted for high drive and level translation is normally included in a memory device to drive the voltage and load levels of an external system bus. With the memory device isolated from the system bus and the local bus carrying voltage levels substantially at internal logic levels of the memory device, no input buffer circuitry is necessary. Furthermore, the dedicated local bus has lower inductive, capacitive and resistive loads, thus reducing the sizing demands on the output buffer circuitry.

As used herein, a signal will have a voltage level compatible with internal logic levels of a device if the expected maximum voltage of the signal is substantially equal to or below the highest acceptable voltage level of the internal logic levels of the device. Elimination or reduction of buffer circuitry further facilitates semiconductor real estate efficiencies approaching those of a single-chip ASIC. Furthermore, electronic systems containing memory and logic devices in accordance with the various embodiments have lower power consumption than typical multiple-device systems as communication between the memory device and the logic device is at voltage levels substantially at internal logic levels rather than higher system bus levels.

While the local bus operates at voltages compatible with internal logic levels of the memory device such that elimination of input buffer circuitry is attainable, it may still be desirable to provide for signal conditioning of one or more of the input signals. Such signal conditioning may include matching impedance between the memory device and the logic device to reduce reflections that become increasingly detrimental at higher transmission frequencies. However, without the need for level translation between system bus voltage levels and the memory device logic levels, the input buffer circuitry can make use of smaller transistors adapted for signal conditioning and substantially incapable of level translation. Again, the reduction in input buffer size facilitates higher real estate efficiencies.

FIG. 2A illustrates a simplified block diagram of an electronic system 200A having a memory device 202A and a logic device 204A, wherein the memory device 202A is coupled to the logic device 204A through a local bus 275. The memory device 202A generally includes a memory core block 110 containing the memory cells and sensing circuitry; a control, logic and interconnect block 112, and an analog block 114 providing the various internal voltage potentials from the supply potential. The logic device 204A generally includes a logic core block 116; a static random access memory (SRAM) block 118 for caching data between the logic core block 116 and the memory core block 110; an input/output (I/O) block 120 for interfacing with the system bus 250; and often a customer-specific block 122 containing customer-specific functionality. It is noted that the functionality of the SRAM block 118 may be replaced by what is termed pseudo-static RAM. In pseudo-static RAM, a dynamic RAM (DRAM) array is automatically refreshed in the background such that it appears functionally as an SRAM array to external devices. This approach allows the use of DRAM technology in place of SRAM technology.

The memory device 202A is coupled to the logic device 204A through a local bus 275. The local bus 275 contains at least one conductive line for electrical communication of signals between the memory device 202A and the logic device 204A. Some common examples of conductive lines include wire bond connections and solder bump connections well known in the art. For one embodiment, the local bus 275 may include one line for each address signal, data signal, and control signal communicated between the memory device 202A and the logic device 204A. For another embodiment, at least a portion of the signals communicated between the memory device 202A and the logic device 204A are multiplexed such that at least one line of the local bus 275 services two or more signals.

FIG. 2B illustrates a functional block diagram of a memory device 202B coupled to a logic device 204B of an electronic system 200B in accordance with one embodiment of the invention. FIG. 2B provides alternative detail of the memory device to more clearly describe the function of the local bus 275. The memory device 202B may, for example, be fabricated as an integrated circuit device on a semiconductor die of a semiconductor wafer. The memory device 202B includes a memory array 206. The memory cells (not shown) of the memory array 206 may be non-volatile floating-gate memory cells, such as in a flash memory device. Row access circuitry 210 and column access circuitry 212 are provided to decode address signals provided on address signal lines A0-Ax 214 from the local bus 275. Row access circuitry 210 and column access circuitry 212 provide access to the memory cells of the memory array 206 in response to the decoded address signals.

An address latch circuit 208 is provided to latch the externally-applied address signals prior to decoding. Data output driver circuit 220 is included for outputting data over a plurality of data (DQ) signal lines 226 to the logic device 204B across the local bus 275. A data latch 224 is provided between the DQ signal lines 226 and the memory array 206 for storing data values (to be written to a memory cell) received on the DQ signal lines 226 from the logic device 204B across the local bus 275.

Command control circuit 216 decodes control signals provided on control signal lines 228 from the logic device 204B across local bus 275. The control signals are used to control the operations on the memory array 206, including data read, data write, and erase operations. For one embodiment, the memory device 202B is a nominally-buffered device. As used herein, a device or signal line will be nominally-buffered if it lacks buffer circuitry adapted for level translation, such as between a system bus level and an internal logic level, yet still permits other buffer circuitry for internal signal conditioning, such as impedance matching. For a further embodiment, the memory device 202B is a non-buffered device as no input buffer circuitry is coupled to the DQ signal lines 226, the address signal lines 214 or the control signal lines 228.

In a typical memory device, input buffer circuitry for level translation is provided between the DQ signal lines 226 and the data latch 224, between the address signal lines 214 and the address latch circuit 208, and between the control signal lines 228 and the command control circuit 216. Such level-translating input buffer circuitry is generally included to buffer or protect a device from input voltages that are detrimentally higher than the internal logic levels, such as those that might be utilized across a general-purpose system bus. As communications across the local bus 275 between the memory device 202B and the logic device 204B are at voltage levels associated with the internal logic levels of the devices, no input buffering is necessary for protection of the devices. However, as noted previously, impedance matching or other signal conditioning without level translation may be desirable. For one embodiment, at least one DQ signal line 226, at least one address signal line 214, and/or at least one control signal line 228 is nominally-buffered. For a further embodiment, at least one DQ signal line 226, at least one address signal line 214 and/or at least one control signal line 228 is non-buffered.

In addition to a reduction in input buffer circuitry, buffer circuitry of the data output driver circuit 220 may also be reduced. The local bus 275 as described herein has lower inductive, capacitive and resistive loads than a corresponding system bus 250. As such, the data output driver circuit 220 would be called upon to drive a significantly smaller load. Because of the smaller load, smaller output transistors may be used leading to lower power consumption and higher die efficiencies.

The memory device 202B has been simplified to facilitate a basic understanding of the features of the memory. A more detailed understanding of memory device functional components is known to those skilled in the art.

FIGS. 3A-3C are a top, side and bottom view, respectively, of an electronic system 300 as a stacked package or multi-chip module in accordance with one embodiment of the invention. For the electronic system 300, a logic device 204 is mounted to a memory device 202. The memory device 202 may further be mounted to a printed circuit board (PCB) or other carrier 360. The memory device 202 and the logic device 204 each have bonding pads or other coupling areas for providing electrical communication to various internal circuitry, such as control signal lines, address signal lines and DQ signal lines. The coupling areas 362 of the memory device 202 and the coupling areas 364 of the logic device 204 are depicted as bonding pads. Coupling areas 362 are coupled to coupling areas 364 through one or more direct connections 366. The direct connections 366 collectively make up the local bus.

The direct connections 366 are depicted as wire bonds, although other connections are known such as solder bump connections. The direct connections 366 have no intervening devices or other drops between a coupling area 362 of the memory device 202 and its corresponding coupling area 364 of the logic device 204. Advantageously, each direct connection 366 can thus be physically small, having relatively low power dissipation compared to a typical system bus. In general, the length of a typical system bus is at least one order of magnitude greater than the length of the direct connections 366. For one embodiment, each direct connection 366 is less than about 2 mm in length. For a further embodiment, each direct connection 366 is less than about 1 mm in length. Collectively, direct connections 366 form the dedicated local bus between the memory device 202 and the logic device 204. For one embodiment, the memory device 202 receives an external clock signal and/or power supply potentials from the logic device 204 through the local bus. For another embodiment, the memory device 202 receives an external clock signal and/or power supply potentials through a connection (not shown) to the carrier 360 or other external device.

The arrangement shown in FIGS. 3A-3C is particularly advantageous where the logic device 204 is smaller than the memory device 202, facilitating placement of coupling areas 362 and 364 around the perimeter of each corresponding device. Other arrangements are possible for electronic systems in accordance with the invention, including placing the memory device 202 on top of the logic device 204, mounting the memory device 202 and the logic device 204 on opposite sides of a carrier 360, and placing the memory device 202 and the logic device 204 substantially in the same plane, either adjoining or laterally spaced apart. In each case, coupling areas 362 and 364 should be accessible to simplify manufacture of the electronic system.

FIGS. 3A-3B further show a portion of coupling areas 364 of the logic device 204 coupled to coupling areas 368 of the carrier 360 through connections 370. The connections 370, as with the direct connections 366, are depicted as wire bonds. Such coupling areas 364 may be coupled to a system bus through the connections 370 for communication with external devices or user interfaces, such as a keyboard, buzzer, microphone, speaker, display, etc., of a wireless communication system. Such coupling areas 364 may further receive power supply potentials or other external signals, such as an external clock signal, through such connections 370. The connections 370 are generally coupled to these external devices, external signals or power supply potentials though external connections 372, depicted in FIGS. 3B-3C as solder bump connections. The portion of coupling areas 364 of the logic device 204 coupled to connections 370 is separate and distinct from the portion of coupling areas 364 of the logic device 204 coupled to direct connections 366. As shown in FIG. 3B, the electronic system 300 generally incorporates an encapsulant 374 to protect the devices and connections from such things as mechanical shock, harmful atmospheres, and electrical shorts.

In electronic systems in accordance with the invention, designers may further eliminate electrostatic discharge (ESD) protection in the memory device. As an example, in the electronic system 300 of FIGS. 3A-3B, the memory device 202 is isolated from a system bus by the interposing logic device 204. Furthermore, the direct connections 366 are insulated from external discharges by the encapsulant 374. Thus, the memory device 202 may be devoid of ESD protection, relying instead on any ESD protection contained in the logic device 204 or on the carrier 360.

With such close integration of a logic device and memory device as described herein, additional embodiments may further eliminate logic functions from the memory device, leaving only the memory array and access circuitry. The high bit-width, high-speed communication facilitated by the dedicated local bus allows use of the logic device to provide all logic functions to the memory device, such as command interpretation and address decoding. In this manner, decoded address signals may be sent from the logic device to the memory device for access of the memory array without further address decoding. Similarly, decoded command signals may be sent from the logic device to the memory device for control of operations on the memory array without further command interpretation.

CONCLUSION

Memory devices and electronic systems having a memory device and a logic device have been described facilitating increased performance, reduced power consumption and reduced cost. Memory devices of the various embodiments are adapted for communication across a dedicated local bus at voltages compatible with internal logic levels, thereby facilitating elimination or reduction of buffer circuitry. The various embodiments facilitate increased performance by supporting increased communication rates and larger word sizes between a memory device and a logic device. The various embodiments facilitate reduced power consumption by lowering voltages for communications between a separate memory device and a separate logic device to levels compatible with internal logic levels of the devices. The various embodiments facilitate reduced cost by allowing the memory portion of an electronic system to be produced using a relatively low-cost memory fabrication technique without detrimental impact on the logic portion of the electronic system, and by reducing semiconductor real estate usage to levels comparable to a single-chip ASIC device.

The various embodiments of the invention and their adaptation for the use of a local bus for communications between a memory device and a logic device provide certain additional advantages. The local bus between the memory device and the logic device is generally orders of magnitude lower in length relative to a system bus, thereby resulting in lower power dissipation through lower resistive losses. In addition to lower power dissipation relative to a system bus, the local bus further provides faster communication rates. The local bus, due to its relative length and lack of intervening devices or drops, will exhibit lower ringing, thereby improving communication reliability and facilitating higher clock frequencies between the memory device and the logic device. The local bus can also provide faster communications through the use of higher levels of parallelism. As an example, an electronic system having a memory device and logic device each supporting a 64-bit word can utilize a local bus including 64 DQ signal lines, despite having a system bus that might be limited to a 16-bit word. In this manner, the 64-bit word can be transferred between the memory device and the logic device in a single transfer of 64 bits, rather than four sequential transfers of 16 bits each.

By limiting the high-speed communication between a memory device and a logic device to the dedicated local bus, the system bus can be optimized for the relatively lower communication rates necessary for communications between the logic device and external devices or user interfaces. Accordingly, the bit width of the system bus may be reduced without detrimentally impacting system performance. The number of connections between the logic device and these external devices and user interfaces via the system bus can also be reduced, thereby reducing the magnitude of buffer circuitry required on the logic device, i.e., buffer circuitry for level translating can be limited to only those connections of the logic device coupled to the system bus.

Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many adaptations of the invention will be apparent to those of ordinary skill in the art. Accordingly, this application is intended to cover any adaptations or variations of the invention. It is manifestly intended that this invention be limited only by the following claims and equivalents thereof. 

1. A memory device, comprising: a memory array; and at least one nominally-buffered signal line, substantially incapable of level translation, for communication between the memory array and an external device; wherein the memory device is devoid of logic functions capable of command interpretation; and wherein the memory device is devoid of logic functions capable of address decoding.
 2. The memory device of claim 1, wherein the at least one nominally-buffered signal line comprises: at least one control signal line for receiving control signals from the external device; at least one address signal line for receiving address signals from the external device for accessing a portion of the memory array in response to the control signals; and at least one data signal line for receiving data signals from the external device for writing to the accessed portion of the memory array.
 3. The memory device of claim 1, wherein the at least one nominally-buffered signal line is a non-buffered signal line.
 4. The memory device of claim 1, wherein the at least one nominally-buffered signal line is multiplexed to service more than one signal.
 5. The memory device of claim 1, wherein the at least one nominally-buffered signal line comprises: a plurality of nominally-buffered data signal lines; a plurality of nominally-buffered address signal lines; and a plurality of nominally-buffered control signal lines.
 6. The memory device of claim 1, wherein the at least one nominally-buffered signal line is a data signal line.
 7. The memory device of claim 1, wherein the at least one nominally-buffered signal line is an address signal line.
 8. The memory device of claim 1, wherein the at least one nominally-buffered signal line is a control signal line.
 9. A memory device, comprising: a memory array; and at least one control signal line for receiving decoded control signals from an external device to control operations on the memory array; at least one address signal line for receiving decoded address signals from the external device; wherein the memory device is devoid of logic functions capable of command interpretation; and wherein the memory device is devoid of logic functions capable of address decoding.
 10. The memory device of claim 9, wherein each address signal line is a nominally-buffered signal line.
 11. The memory device of claim 9, wherein the at least one address signal line is a non-buffered signal line.
 12. The memory device of claim 9, wherein each control signal line is a nominally-buffered signal line.
 13. The memory device of claim 9, wherein the at least one control signal line is a non-buffered signal line.
 14. A memory device, comprising: a memory array; and at least one control signal line for receiving decoded control signals from an external device to control operations on the memory array; at least one address signal line for receiving decoded address signals from the external device; wherein the memory device is devoid of logic functions capable of command interpretation; wherein the memory device is devoid of logic functions capable of address decoding; and wherein each control signal line and address signal line is substantially incapable of level translation.
 15. A memory device, comprising: a memory array; at least one control signal line for receiving control signals from an external device; at least one address signal line for receiving address signals from the external device for accessing a portion of the memory array in response to the control signals; and at least one data signal line for communicating data signals between the external device and an accessed portion of the memory array; wherein at least one control signal line, address signal line or data signal line is substantially incapable of level translation; wherein the memory device is devoid of logic functions capable of command interpretation; and wherein the memory device is devoid of logic functions capable of address decoding.
 16. A memory device, comprising: a memory array; at least one control signal line for receiving control signals from an external device; at least one address signal line for receiving address signals from the external device for accessing a portion of the memory array in response to the control signals; and at least one data signal line for communicating data signals between the external device and an accessed portion of the memory array; wherein at least one control signal line, address signal line or data signal line is adapted for use with voltage levels that are compatible with internal logic levels of the memory array; wherein at least one control signal line, address signal line or data signal line is a nominally-buffered signal line; wherein at least one control signal line, address signal line or data signal line is substantially incapable of level translation; wherein the memory device is devoid of logic functions capable of command interpretation; and wherein the memory device is devoid of logic functions capable of address decoding.
 17. An electronic system, comprising: a logic device for coupling to a system bus; a memory device separate from the logic device; and a local bus coupled between the logic device and the memory device; wherein the memory device comprises at least one nominally-buffered signal line coupled to the local bus; and wherein the at least one nominally-buffered signal line is multiplexed to service more than one signal.
 18. The electronic system of claim 17, wherein the at least one nominally-buffered signal line is a non-buffered signal line.
 19. The electronic system of claim 17, wherein the at least one nominally-buffered signal line is substantially incapable of level translation.
 20. An electronic system, comprising: a logic device for coupling to a system bus; a memory device separate from the logic device; and a local bus coupled between the logic device and the memory device; wherein the memory device includes at least one nominally-buffered signal line coupled to the local bus; wherein the memory device is devoid of logic functions capable of command interpretation; wherein the memory device is devoid of logic functions capable of address decoding; and wherein the at least one nominally-buffered signal line comprises: a plurality of nominally-buffered data signal lines; a plurality of nominally-buffered address signal lines; and a plurality of nominally-buffered control signal lines.
 21. An electronic system, comprising: a logic device for coupling to a system bus; a memory device separate from the logic device; and a local bus coupled between the logic device and the memory device; wherein the memory device includes at least one nominally-buffered signal line coupled to the local bus; wherein the memory device is devoid of logic functions capable of command interpretation; wherein the memory device is devoid of logic functions capable of address decoding; and wherein the memory device comprises a memory array and the at least one nominally-buffered signal line comprises: at least one control signal line for receiving control signals from the logic device; at least one address signal line for receiving address signals from the logic device for accessing a portion of the memory array in response to the control signals; and at least one data signal line for receiving data signals from the logic device for writing to the accessed portion of the memory array.
 22. An electronic system, comprising: a logic device for coupling to a system bus; a memory device separate from the logic device; and a local bus coupled between the logic device and the memory device; wherein the memory device comprises: at least one control signal line for receiving control signals from the logic device; at least one address signal line for receiving address signals from the logic device for accessing a portion of the memory array in response to the control signals; and at least one data signal line for receiving data signals from the logic device for writing to the accessed portion of the memory array; wherein the memory device is devoid of logic functions capable of command interpretation; wherein the memory device is devoid of logic functions capable of address decoding; and wherein each control signal line, address signal line, and data signal line is substantially incapable of level translation.
 23. An electronic system, comprising: a logic device for coupling to a system bus; a memory device separate from the logic device; and a local bus coupled between the logic device and the memory device; wherein the memory device comprises: a memory array; at least one control signal line for receiving control signals from the logic device; at least one address signal line for receiving address signals from the logic device for accessing a portion of the memory array in response to the control signals; and at least one data signal line for communicating data signals between the logic device and an accessed portion of the memory array; wherein at least one control signal line, address signal line or data signal line is adapted for use with voltage levels that are compatible with internal logic levels of the memory array; and wherein at least one control signal line, address signal line or data signal line is a nominally-buffered signal line.
 24. The electronic system of claim 23, wherein at least one control signal line, address signal line or data signal line is substantially incapable of level translation.
 25. The electronic system of claim 23, wherein the memory device is devoid of logic functions capable of command interpretation.
 26. The electronic system of claim 23, wherein the memory device is devoid of logic functions capable of address decoding.
 27. An electronic system, comprising: a logic device for coupling to a system bus; a memory device separate from the logic device; and a local bus coupled between the logic device and the memory device; wherein the memory device comprises: a memory array; at least one control signal line for receiving control signals from the logic device; at least one address signal line for receiving address signals from the logic device for accessing a portion of the memory array in response to the control signals; and at least one data signal line for communicating data signals between the logic device and an accessed portion of the memory array; wherein at least one control signal line, address signal line or data signal line is adapted for use with voltage levels that are compatible with internal logic levels of the memory array; wherein at least one control signal line, address signal line or data signal line is a nominally-buffered signal line; wherein at least one control signal line, address signal line or data signal line is substantially incapable of level translation; wherein the memory device is devoid of logic functions capable of command interpretation; and wherein the memory device is devoid of logic functions capable of address decoding. 